University of Southern California
MS in Electrical Engineering · GPA 4.0/4.0
Los Angeles, USAAcademic profile
Qinyan Zeng
M.S. student in Electrical Engineering at the University of Southern California, working in ASIC implementation, RTL design, physical design, timing analysis, and custom CMOS systems.
Research statement
Research and engineering interests
My work follows hardware systems across abstraction levels: transistor-level custom design, synthesizable RTL, verification, timing constraints, physical implementation, and evidence-based evaluation after extraction or routing.
Tools & methods
Verilog · SystemVerilog · Python · Matlab · Cadence Virtuoso · Cadence Innovus · Synopsys Design Compiler · Questa · VCS · LibreLane · OpenROAD · Tcl · SDC · STA
Education
Academic appointments and degrees
University of Electronic Science and Technology of China
MS Research · National Key Laboratory of Wireless Communications
Chengdu, ChinaSouthwest Jiaotong University & University of Leeds
BS in Electronic and Electrical Engineering · First-Class Honours · Major GPA 3.9/4.0
Chengdu, ChinaSelected coursework
Computer Systems OrganizationMOS VLSI Circuits DesignVLSI System DesignMicroprocessors and Programmable LogicComputer Architecture