Project categories
Engineering projects
Projects are organized by physical design, RTL design, and custom CMOS or memory design. Each record opens into a dedicated technical page with implementation scope, methodology, verification, results, and available artifacts.
Technical portfolio
10 independent engineering records
Physical Design & ASIC Implementation
Multi-Clock SRAM ASIC Implementation
An RTL-to-GDSII implementation with four SRAM macros, clock gating and division, pipelined arithmetic, multi-clock SDC, and post-route checks.
ASIC · Physical Design · Jun–Aug 2026 · SystemVerilog, Design Compiler, Cadence Innovus, Tcl, SDC
LSTM Accelerator: RTL-to-GDSII ASIC Implementation
A 16-lane INT8/Q1.7 LSTM accelerator with an 8×8 signed MAC, FSM control, LUT activations, Python golden vectors, and clean GF180MCU GDSII.
Hardware Accelerator · ASIC · May–Aug 2026 · SystemVerilog, Python, LibreLane, OpenROAD, GF180MCU
RTL Design & Computer Architecture
RISC-V Five-Stage Pipeline CPU
A synthesizable in-order five-stage RISC-V CPU with hazard detection and forwarding for RAW and memory-related dependencies.
RTL · Computer Architecture · 2025–2026 · Verilog, SystemVerilog, RISC-V, Testbench
Configurable UART Transmitter and Receiver
A synthesizable UART TX/RX supporting 5–8 data bits, odd/even parity, stop-bit options, 16× receive oversampling, and 50 verified configurations.
RTL · Digital Communications · 2025–2026 · Verilog, SystemVerilog, FSM, Testbench
Custom CMOS & Memory Design
8-bit Comparator: Custom CMOS Implementation
An 8-bit comparator carried from logic simplification and transistor sizing through schematic, layout, physical verification, extraction, and post-layout analysis.
Custom CMOS · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Ripple-Carry Adder: Custom CMOS Implementation
A transistor-level 16-bit ripple-carry adder implemented and evaluated through extracted post-layout analysis.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Carry-Skip Adder: Custom CMOS Implementation
A 16-bit carry-skip adder designed at transistor level, laid out, extracted, and assessed on its post-layout critical path.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Carry-Lookahead Adder: Custom CMOS Implementation
A 16-bit carry-lookahead adder implemented through custom layout and extracted post-layout critical-path analysis.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Multiply–Accumulate Unit
A transistor-level 16-bit MAC combining Radix-4 Booth encoding, 6-to-2 compression, and a final carry-lookahead adder.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, Radix-4 Booth, 6-to-2 compressor, CLA, DRC
512-bit SRAM Macro with Four-Way Bank Interleaving
A 512-bit custom SRAM macro with 16-bit words, four-way bank interleaving, peripheral circuits, and verified operation up to 500 MHz.
Custom Memory · 2025–2026 · Cadence Virtuoso, SRAM, DRC, LVS, PEX