University of Southern California
M.S. in Electrical Engineering · GPA 4.0/4.0
M.S. Student in Electrical Engineering
Qinyan Zeng
ASIC Design · RTL Design · Physical Design · VLSI Systems
I am an electrical engineering graduate student at the University of Southern California. My work spans custom CMOS design, synthesizable RTL, verification, synthesis, static timing analysis, and physical implementation from floorplanning through GDSII.
Projects
Physical Design & ASIC Implementation
Multi-Clock SRAM ASIC Implementation
Integrated four SRAM macros into a multi-clock subsystem and carried the design from synthesis and SDC through Innovus routing and GDS export.
ASIC · Physical Design · Jun–Aug 2026 · SystemVerilog, Design Compiler, Cadence Innovus, Tcl, SDC
LSTM Accelerator: RTL-to-GDSII ASIC Implementation
Mapped a 16-lane quantized LSTM datapath into a 22-pin GF180MCU macro and verified the RTL against a Python model before physical implementation.
Hardware Accelerator · ASIC · May–Aug 2026 · SystemVerilog, Python, LibreLane, OpenROAD, GF180MCU
RTL Design & Computer Architecture
RISC-V Five-Stage Pipeline CPU
Implemented a 32-bit five-stage RISC-V core with forwarding and a one-cycle load-use stall, then verified dependency cases in simulation.
RTL · Computer Architecture · 2025–2026 · Verilog, SystemVerilog, RISC-V, Testbench
Tomasulo-Based Out-of-Order Execution CPU
Implemented a compact Tomasulo backend with register renaming, reservation stations, Common Data Bus wakeup, and in-order ROB commit.
RTL · Computer Architecture · 2025–2026 · Verilog, Tomasulo algorithm, Reservation stations, Reorder buffer, Waveform verification
Configurable UART Transmitter and Receiver
Designed configurable UART TX/RX RTL with 16× receive oversampling and tested 50 frame configurations from 4.8 to 57.6 kbaud.
RTL · Digital Communications · 2025–2026 · Verilog, SystemVerilog, FSM, Testbench
Custom CMOS & Memory Design
Custom CMOS Comparator and Adder Circuit Design
Designed an 8-bit comparator and three 16-bit adders in Virtuoso, then compared schematic and extracted post-layout timing.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Multiply–Accumulate Unit
Built a transistor-level 16-bit MAC around Radix-4 Booth recoding, compressor reduction, a carry-lookahead adder, and registered accumulation.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, Radix-4 Booth, 6-to-2 compressor, CLA, DRC
512-bit SRAM Macro with Four-Way Bank Interleaving
Designed a 512-bit, four-bank SRAM macro with a 16-bit interface and the complete read, write, sensing, and output path.
Custom Memory · 2025–2026 · Cadence Virtuoso, SRAM, DRC, LVS, PEX
Education
University of Electronic Science and Technology of China
M.S. Research · Information and Communication Engineering
Southwest Jiaotong University & University of Leeds
B.S. in Electronic and Electrical Engineering · First-Class Honours · Major GPA 3.9/4.0
Selected publications
- [1]
Q. Zeng and X. Cheng, “Fundamental Localization Limits of Quantized Uplink mmWave MIMO Systems in Moving Scenarios,” Proc. IEEE/CIC Int. Conf. Commun. China (ICCC), 2023. IEEE Xplore ↗
- [2]
Y. Guan, Q. Zeng, and X. Cheng, “Position Estimation in Massive MIMO Systems With Low-Resolution ADCs,” Proc. Int. Conf. Wireless Commun. Signal Process. (WCSP), 2023. IEEE Xplore ↗
Certification
Cadence RTL-to-GDSII Flow v7.0
Cadence Design Systems