University of Southern California
M.S. in Electrical Engineering · GPA 4.0/4.0
M.S. Student in Electrical Engineering
Qinyan Zeng
ASIC Design · RTL Design · Physical Design · VLSI Systems
I am an electrical engineering graduate student at the University of Southern California. My work spans custom CMOS design, synthesizable RTL, verification, synthesis, static timing analysis, and physical implementation from floorplanning through GDSII.
Projects
Complete technical records expanding the project descriptions in my résumé.
[P01]Project details →[P02]Project details →[P03]Project details →[P04]Project details →[P05]Project details →[P06]Project details →[P07]Project details →[P08]Project details →[P09]Project details →[P10]Project details →[R01]Project details →[R02]Project details →
8-bit Comparator: Custom CMOS Implementation
An 8-bit comparator carried from logic simplification and transistor sizing through schematic, layout, physical verification, extraction, and post-layout analysis.
Custom CMOS · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Ripple-Carry Adder: Custom CMOS Implementation
A transistor-level 16-bit ripple-carry adder implemented and evaluated through extracted post-layout analysis.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Carry-Skip Adder: Custom CMOS Implementation
A 16-bit carry-skip adder designed at transistor level, laid out, extracted, and assessed on its post-layout critical path.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Carry-Lookahead Adder: Custom CMOS Implementation
A 16-bit carry-lookahead adder implemented through custom layout and extracted post-layout critical-path analysis.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, CMOS, DRC, LVS, PEX
16-bit Multiply–Accumulate Unit
A transistor-level 16-bit MAC combining Radix-4 Booth encoding, 6-to-2 compression, and a final carry-lookahead adder.
Custom CMOS · Arithmetic · 2025–2026 · Cadence Virtuoso, Radix-4 Booth, 6-to-2 compressor, CLA, DRC
512-bit SRAM Macro with Four-Way Bank Interleaving
A 512-bit custom SRAM macro with 16-bit words, four-way bank interleaving, peripheral circuits, and verified operation up to 500 MHz.
Custom Memory · 2025–2026 · Cadence Virtuoso, SRAM, DRC, LVS, PEX
Multi-Clock SRAM ASIC Implementation
An RTL-to-GDSII implementation with four SRAM macros, clock gating and division, pipelined arithmetic, multi-clock SDC, and post-route checks.
ASIC · Physical Design · Jun–Aug 2026 · SystemVerilog, Design Compiler, Cadence Innovus, Tcl, SDC
LSTM Accelerator: RTL-to-GDSII ASIC Implementation
A 16-lane INT8/Q1.7 LSTM accelerator with an 8×8 signed MAC, FSM control, LUT activations, Python golden vectors, and clean GF180MCU GDSII.
Hardware Accelerator · ASIC · May–Aug 2026 · SystemVerilog, Python, LibreLane, OpenROAD, GF180MCU
RISC-V Five-Stage Pipeline CPU
A synthesizable in-order five-stage RISC-V CPU with hazard detection and forwarding for RAW and memory-related dependencies.
RTL · Computer Architecture · 2025–2026 · Verilog, SystemVerilog, RISC-V, Testbench
Configurable UART Transmitter and Receiver
A synthesizable UART TX/RX supporting 5–8 data bits, odd/even parity, stop-bit options, 16× receive oversampling, and 50 verified configurations.
RTL · Digital Communications · 2025–2026 · Verilog, SystemVerilog, FSM, Testbench
Fundamental Localization Limits of Quantized Uplink mmWave MIMO Systems in Moving Scenarios
A peer-reviewed conference paper on fundamental localization limits in quantized uplink mmWave MIMO systems under motion.
Research Publication · ICCC · 2023 · mmWave MIMO, Localization, Quantization, Moving scenarios
Position Estimation in Massive MIMO Systems With Low-Resolution ADCs
A peer-reviewed conference paper on position estimation in massive-MIMO systems using low-resolution analog-to-digital converters.
Research Publication · WCSP · 2023 · Massive MIMO, Position estimation, Low-resolution ADCs
Education
University of Electronic Science and Technology of China
M.S. Research · National Key Laboratory of Wireless Communications
Southwest Jiaotong University & University of Leeds
B.S. in Electronic and Electrical Engineering · First-Class Honours · Major GPA 3.9/4.0
Selected publications
- [1]
Q. Zeng and X. Cheng, “Fundamental Localization Limits of Quantized Uplink mmWave MIMO Systems in Moving Scenarios,” Proc. IEEE/CIC Int. Conf. Commun. China (ICCC), 2023. IEEE Xplore ↗
- [2]
Y. Guan, Q. Zeng, and X. Cheng, “Position Estimation in Massive MIMO Systems With Low-Resolution ADCs,” Proc. Int. Conf. Wireless Commun. Signal Process. (WCSP), 2023. IEEE Xplore ↗