16-bit Multiply–Accumulate Unit
This MAC was built as a transistor-level datapath rather than as a behavioral multiply operator. It combines Booth recoding, compressor-based partial-product reduction, a carry-lookahead final adder, and a feedback register for accumulation.
Booth recoding→Compressor tree→Carry-lookahead adder→Feedback register
Partial products
Radix-4 Booth recoding examines the multiplier two bits at a time and selects signed multiples of the multiplicand. Reducing the number of partial-product rows also reduces the amount of work required in the compression tree.
Compression and accumulation
A tree of 3:2 and 6:2 compressors reduces the partial products to two rows. A carry-lookahead adder resolves the final sum, and the registered feedback path performs the accumulated operation on the next cycle.
Physical implementation
I completed block-level and integrated simulation, custom layout, DRC, LVS, parasitic extraction, and post-layout timing checks. The critical path was traced across Booth generation, compression, final addition, and the extracted RC network.
Cadence Virtuoso · Radix-4 Booth · 6-to-2 compressor · CLA · DRC · LVS · PEX