Detailed Project Report · Custom CMOS · Arithmetic · 2025–2026
16-bit Multiply–Accumulate Unit
Abstract
The MAC project extends the custom arithmetic work to a hierarchical multiply–accumulate datapath. Partial products are formed with Radix-4 Booth encoding, reduced with 6-to-2 compressors, and resolved with a carry-lookahead adder before physical verification and extraction.
Keywords—Cadence Virtuoso, Radix-4 Booth, 6-to-2 compressor, CLA, DRC, LVS, PEX.
I. Project summary
| Datapath | 16-bit MAC |
|---|---|
| Encoding | Radix-4 Booth |
| Reduction | 6-to-2 compressors |
| Final adder | Carry-lookahead |
II. Scope and contribution
- Constructed the transistor-level MAC hierarchy.
- Integrated Booth encoding, compressor reduction, and final addition.
- Completed layout, DRC, LVS, and PEX.
III. Methodology
- Radix-4 partial-product encoding
- Compressor-tree reduction
- Carry-lookahead final addition
- Hierarchical custom layout
IV. Verification
- Block-level and integrated functional simulation.
- DRC and LVS.
- PEX-based post-layout verification.
V. Reported results
- Completed the 16-bit MAC from transistor-level schematic through extracted layout.
- Closed the stated physical verification flow.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Datapath hierarchy
- Booth encoder
- Compressor stages
- Integrated layout
- DRC/LVS/PEX summary