Detailed Project Report · RTL · Digital Communications · 2025–2026
Configurable UART Transmitter and Receiver
Abstract
The UART implements configurable transmit and receive state machines, baud-rate clock division, frame generation and decoding, parity checking, and receive-error reporting. The receiver samples at 16 times the configured baud rate, and verification spans 50 combinations of data length, parity, and stop-bit configuration.
Keywords—Verilog, SystemVerilog, FSM, Testbench.
I. Project summary
| Data length | 5–8 bit |
|---|---|
| Parity | Odd / even |
| Receive sampling | 16× oversampling |
| Baud range | 4.8–57.6 kbaud |
| Verified configurations | 50 |
II. Scope and contribution
- Designed configurable TX and RX FSMs.
- Implemented baud generation, oversampling, parity, stop-bit, and error logic.
- Constructed the configuration verification matrix.
III. Methodology
- Parameterized serial framing
- Clock-divider baud generation
- Center-of-bit receive sampling
- Protocol-matrix testing
IV. Verification
- TX/RX functional tests.
- Parity and error-detection cases.
- Fifty data-length/parity/stop-bit combinations.
- Baud-rate coverage from 4.8 to 57.6 kbaud.
V. Reported results
- Completed the synthesizable UART transmitter and receiver.
- Verified 50 protocol configurations.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Frame format
- TX/RX FSMs
- Clock-divider logic
- Waveforms
- Configuration matrix