Custom CMOS Comparator and Adder Circuit Design
I designed the comparator and all three adders in Cadence Virtuoso and kept the device-level flow consistent across the set. That made it possible to compare the logic choices again after layout, when wiring and device parasitics had been included.
Comparator8-bit magnitude comparison with shared equality logic
Ripple carryRegular serial-carry baseline
Carry skipBlock-level carry bypass
Carry lookaheadParallel generate / propagate logic
Comparator
The 8-bit magnitude comparator gives priority to the most significant unequal bit. I evaluated complementary-CMOS logic, shared equality terms, and transmission-gate multiplexers, then used targeted vectors to exercise the longest decision path.
Adder architectures
The 16-bit ripple-carry adder served as the regular serial-carry baseline. The carry-skip version added block bypass paths, while the carry-lookahead version generated carries from propagate and generate terms in parallel.
I compared the designs with critical-path vectors rather than gate count alone. The useful tradeoff was between logic depth, bypass loading, fan-in, and the extra wiring required by parallel carry generation.
Layout and extraction
For each circuit I completed schematic simulation, transistor sizing, custom layout, DRC, LVS, parasitic extraction, and extracted timing simulation. Comparing schematic and extracted waveforms showed how interconnect resistance, diffusion capacitance, and asymmetric loading changed the expected delay.
Cadence Virtuoso · CMOS · DRC · LVS · PEX