Detailed Project Report · Hardware Accelerator · ASIC · May–Aug 2026
LSTM Accelerator: RTL-to-GDSII ASIC Implementation
Abstract
The accelerator implements four LSTM gates using a 16-lane fixed-point datapath, signed 8×8 MAC operations, state registers, LUT-based activation approximation, and an FSM for computation and handshaking. SystemVerilog simulation is checked against Python-generated reference vectors before physical implementation in the GF180MCU LibreLane/OpenROAD flow.
Keywords—SystemVerilog, Python, LibreLane, OpenROAD, GF180MCU, STA.
I. Project summary
| Parallelism | 16 lanes |
|---|---|
| Number format | INT8 / Q1.7 |
| MAC | Signed 8×8 |
| Post-route frequency | 10 MHz |
| Physical result | DRC/LVS clean |
II. Scope and contribution
- Designed the datapath, state storage, and FSM controller.
- Implemented sequential f, i, g, and o gate computation with LUT activations.
- Generated Python golden vectors and built the SystemVerilog testbench.
- Ran the GF180MCU RTL-to-GDSII flow.
III. Methodology
- Fixed-point arithmetic
- Sixteen compute lanes
- LUT activation approximation
- Golden-model comparison
- Open-source physical design flow
IV. Verification
- Python reference-vector comparison.
- Sequencing, arithmetic, state-update, and handshake checks.
- Post-route timing analysis.
- Final DRC and LVS.
V. Reported results
- Achieved the reported 10 MHz post-route result.
- Generated DRC/LVS-clean GDSII.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Architecture
- RTL hierarchy
- Golden-vector flow
- Simulation waveforms
- Routed layout
- Signoff summary