ASIC · Physical Design · Jun–Aug 2026

Multi-Clock SRAM ASIC Implementation

I built this project to work through the backend consequences of a multi-clock RTL design. The subsystem contains four SRAM macros, clock-gating and divider logic, and pipelined arithmetic.

Current statusIn progressFour SRAM macrosPrimary, generated, and gated clocks

Synthesis and constraints

I synthesized the RTL in Synopsys Design Compiler using both standard-cell and SRAM timing libraries. The SDC describes the primary clock together with generated and gated clocks, followed by timing, area, and power checks on the synthesized netlist.

Floorplan through routing

In Innovus I placed the SRAM macros first, then developed the core floorplan, standard-cell placement, and power grid around them. Clock-tree synthesis exposed skew and latency in the physical clock network before signal routing.

Current state

The routed design has been checked for setup and hold timing, routing DRC, and antenna violations.

SystemVerilog · Design Compiler · Cadence Innovus · Tcl · SDC · STA