Detailed Project Report · ASIC · Physical Design · Jun–Aug 2026
Multi-Clock SRAM ASIC Implementation
Abstract
The design integrates four SRAM instances with clock-gating, clock-divider logic, and pipelined arithmetic. A Design Compiler synthesis flow and SDC constraints establish the multi-clock timing environment before macro-aware floorplanning, power planning, CTS, routing, and final physical checks in Innovus.
Keywords—SystemVerilog, Design Compiler, Cadence Innovus, Tcl, SDC, STA.
I. Project summary
| Memory macros | 4 SRAM instances |
|---|---|
| Timing model | Multi-clock |
| Implementation | Synthesis to GDS |
| Final checks | Setup, hold, DRC, antenna |
II. Scope and contribution
- Implemented the multi-clock RTL and pipelined arithmetic.
- Created the standard-cell/SRAM library and synthesis flow.
- Defined SDC constraints and reviewed timing, area, and power.
- Performed floorplanning, placement, power planning, CTS, routing, and GDS generation.
III. Methodology
- Explicit generated/gated-clock constraints
- Macro-aware floorplanning
- Power-grid construction
- Clock-tree synthesis
- Post-route timing analysis
IV. Verification
- Synthesis timing, area, and power reports.
- Constraint checks across the clock environment.
- Post-route setup and hold analysis.
- DRC and antenna checks.
V. Reported results
- Completed synthesis and physical implementation.
- Generated the routed database and GDS after stated timing and physical checks.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Constraint map
- Synthesis reports
- Macro floorplan
- Clock tree
- Post-route timing
- GDS summary