Detailed Project Report · RTL · Computer Architecture · 2025–2026
RISC-V Five-Stage Pipeline CPU
Abstract
This RTL project focuses on control and dependency management in an in-order five-stage processor. Hazard detection and forwarding logic coordinate instruction flow so that data can bypass the register-file path where possible and the pipeline can be held where a dependency remains unresolved.
Keywords—Verilog, SystemVerilog, RISC-V, Testbench.
I. Project summary
| Microarchitecture | Five-stage in-order pipeline |
|---|---|
| Dependency handling | Hazard detection and forwarding |
| Coverage focus | RAW and memory dependencies |
II. Scope and contribution
- Constructed the five-stage pipeline and control path.
- Implemented hazard-detection and forwarding units.
- Built testbench scenarios for pipeline dependencies.
III. Methodology
- In-order pipelining
- Operand forwarding
- Pipeline stall control
- Directed dependency testing
IV. Verification
- Pipeline functional testbench.
- Directed RAW-dependency cases.
- Memory-related dependency cases.
- Forwarding and stall behavior checks.
V. Reported results
- Completed the synthesizable five-stage CPU.
- Verified the stated hazard-detection and forwarding behavior.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Pipeline block diagram
- Control logic
- Dependency tests
- Simulation waveforms