RISC-V Five-Stage Pipeline CPU
I implemented a 32-bit RISC-V core using the classic IF, ID, EX, MEM, and WB pipeline. The main work was keeping control and data aligned while resolving dependencies without stalling instructions that could be forwarded.
Pipeline
The RTL includes the program counter, register file, immediate generator, ALU, memory interfaces, write-back selection, and the four inter-stage registers. Register-write, memory, and result-selection controls travel with the instruction that uses them.
Hazard handling
Forwarding multiplexers select newer results from later stages when a dependent instruction reaches EX before the register file has been updated. A load result arrives too late for that path, so the hazard unit holds the PC and IF/ID register for one cycle and clears the ID/EX controls to insert a bubble.
Simulation
Directed tests cover arithmetic, load and store operations, register write-back, forwarding selections, and load-use stalls. I used cycle-level waveforms to check both the result and the alignment of the associated control signals.
Verilog · SystemVerilog · RISC-V · Testbench