Tomasulo-Based Out-of-Order Execution CPU
This is a compact model of a Tomasulo-style backend rather than a complete speculative processor. Instructions dispatch in order, independent operations may finish out of order, and the reorder buffer commits results in order.
Rename and dispatch→Wakeup and execute→Commit in order
Rename and dispatch
At dispatch, the Register Alias Table maps each destination to a new ROB tag. A source enters its reservation station as either a ready value or a pending tag. Separate stations serve load/store, add/subtract, and multiply/divide units.
Wakeup and execution
Execution units broadcast completed tags and values on the Common Data Bus. Reservation stations capture matching results, and an entry becomes ready once all of its operands are available.
Commit and verification
The ROB stores completed values until the oldest ready entry reaches the head, then writes the result to the architectural register file. I verified RAT remapping, station wakeup, CDB broadcasts, ROB head/tail movement, and in-order commit in simulation waveforms.
Verilog · Tomasulo algorithm · Reservation stations · Reorder buffer · Waveform verification