Detailed Project Report · Custom CMOS · Arithmetic · 2025–2026
16-bit Carry-Lookahead Adder: Custom CMOS Implementation
Abstract
This design uses generate/propagate structure to organize carry computation in a 16-bit custom-CMOS adder. It completes a three-architecture study in which RCA, carry-skip, and carry-lookahead adders share a common physical implementation and verification flow.
Keywords—Cadence Virtuoso, CMOS, DRC, LVS, PEX.
I. Project summary
| Word length | 16 bit |
|---|---|
| Architecture | Carry-lookahead |
| Analysis | Post-layout critical path |
II. Scope and contribution
- Implemented the generate/propagate carry network.
- Built the transistor-level schematic and layout.
- Analyzed the extracted critical path.
III. Methodology
- Generate/propagate logic
- Transistor sizing
- Hierarchical schematic
- Custom layout
- Extracted simulation
IV. Verification
- Functional schematic simulation.
- DRC and LVS.
- PEX-based post-layout analysis.
V. Reported results
- Completed a physically verified 16-bit CLA.
- Completed the three-architecture custom-adder implementation set.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Carry-network schematic
- Layout
- Critical-path waveform
- DRC/LVS/PEX summary