Detailed Project Report · Custom CMOS · Arithmetic · 2025–2026
16-bit Carry-Skip Adder: Custom CMOS Implementation
Abstract
This project introduces carry-skip logic into a 16-bit custom adder to reduce the dependence on a fully serial carry path. The implementation follows the same schematic-to-layout methodology used for the ripple-carry and carry-lookahead designs.
Keywords—Cadence Virtuoso, CMOS, DRC, LVS, PEX.
I. Project summary
| Word length | 16 bit |
|---|---|
| Architecture | Carry-skip |
| Analysis | Post-layout critical path |
II. Scope and contribution
- Implemented carry-propagate and skip behavior.
- Completed the transistor-level schematic and layout.
- Performed post-layout critical-path evaluation.
III. Methodology
- Carry-skip organization
- Transistor sizing
- Hierarchical schematic
- Custom layout
- Extracted simulation
IV. Verification
- Functional schematic simulation.
- DRC and LVS.
- PEX-based post-layout analysis.
V. Reported results
- Completed a physically verified 16-bit carry-skip adder.
- Produced extracted evidence suitable for architecture comparison.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Schematic
- Layout
- Skip-path waveform
- DRC/LVS/PEX summary