Qinyan ZengEmail

Detailed Project Report · Custom CMOS · Arithmetic · 2025–2026

16-bit Ripple-Carry Adder: Custom CMOS Implementation

Qinyan Zeng
Department of Electrical and Computer Engineering
University of Southern California · qyzeng.work@gmail.com

Abstract

The ripple-carry adder is one of three 16-bit adder architectures implemented under the same custom-CMOS workflow. Keeping the implementation and verification path consistent makes its critical-path behavior directly interpretable alongside carry-skip and carry-lookahead structures.

Keywords—Cadence Virtuoso, CMOS, DRC, LVS, PEX.

I. Project summary

Word length16 bit
ArchitectureRipple-carry
AnalysisPost-layout critical path

II. Scope and contribution

  • Implemented the full-adder chain at transistor level.
  • Constructed schematic and physical layout.
  • Evaluated the extracted critical path.

III. Methodology

  1. Full-adder construction
  2. Cascaded carry path
  3. Transistor sizing
  4. Custom layout
  5. Extracted simulation

IV. Verification

  • Functional schematic simulation.
  • DRC and LVS.
  • PEX-based post-layout delay analysis.

V. Reported results

  • Completed a physically verified 16-bit RCA.
  • Established an extracted result for comparison with the other adder architectures.

VI. Artifacts and data availability

The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:

  • Hierarchical schematic
  • Layout
  • Critical-path waveform
  • DRC/LVS/PEX summary