512-bit SRAM Macro with Four-Way Bank Interleaving
I started with a 6T bitcell and extended the design into a complete 512-bit macro. The final organization uses four interleaved banks behind a 16-bit word interface and includes the peripheral circuits needed for actual read and write operation.
- Capacity
- 512 bit
- Word size
- 16 bit
- Organization
- 4 banks · 8 rows/bank · 16 cells/row
- Single-cell timing test
- 2 ns minimum period (500 MHz)
Row decode→Interleaved arrays→Column select→Sense and register
Organization
Each bank contains eight rows of sixteen cells. A 3-to-8 decoder selects the wordline, and a decoded 4-to-1 transmission-gate multiplexer connects the selected bank to the read path.
Read and write path
The macro includes bitline precharge, write drivers, a differential sense amplifier, an output latch, and an output register. Their control timing determines when a bitline may be written, sensed, and captured safely.
Timing checks
I used separate bitcell and full-array testbenches for precharge, write, read, sensing, address changes, and repeated writes to the same address. Wordline and bitline capacitance were included in the array tests.
The bitcell testbench operated with a minimum 2 ns period. For the full array, I measured decoder delay, bitline development, and sense-amplifier delay separately instead of treating the bitcell frequency as a macro-level result.
Cadence Virtuoso · SRAM · DRC · LVS · PEX · Timing simulation