Detailed Project Report · Custom Memory · 2025–2026
512-bit SRAM Macro with Four-Way Bank Interleaving
Abstract
This project develops a complete SRAM macro rather than an isolated bitcell. The design combines a four-way bank-interleaved array with row and column decoding, write drivers, sense amplifiers, output latches, and registers. Verification progresses from a single-bitcell testbench to the full array.
Keywords—Cadence Virtuoso, SRAM, DRC, LVS, PEX, Timing simulation.
I. Project summary
| Capacity | 512 bit |
|---|---|
| Word size | 16 bit |
| Organization | Four-way bank interleaving |
| Reported maximum frequency | 500 MHz |
II. Scope and contribution
- Designed the bitcell array organization and bank interleaving.
- Implemented row/column decoders, write drivers, sensing, latch, and output register circuitry.
- Built bitcell and full-array testbenches.
III. Methodology
- Bitcell-first verification
- Bank-interleaved organization
- Peripheral-circuit integration
- Full-array timing simulation
IV. Verification
- Single-bitcell functional testbench.
- Full-array read/write testbench.
- DRC, LVS, and PEX.
- Functional and timing verification of the integrated macro.
V. Reported results
- Completed the custom 512-bit SRAM macro and peripheral circuitry.
- Verified operation at a reported maximum frequency of 500 MHz.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Bitcell schematic/layout
- Array floorplan
- Peripheral schematics
- Full-array waveforms
- Timing summary