Detailed Project Report · Custom CMOS · 2025–2026
8-bit Comparator: Custom CMOS Implementation
Abstract
This work implements an 8-bit comparison function at transistor level. The project record covers the complete custom-design path rather than reporting schematic simulation alone: logic formulation, device sizing, layout construction, DRC/LVS, parasitic extraction, and post-layout evaluation.
Keywords—Cadence Virtuoso, CMOS, DRC, LVS, PEX.
I. Project summary
| Design level | Transistor level |
|---|---|
| Function | 8-bit comparison |
| Flow | Schematic to post-layout |
II. Scope and contribution
- Simplified the comparator logic before transistor-level implementation.
- Selected transistor sizes and constructed the schematic.
- Completed layout and extracted-view analysis.
III. Methodology
- Logic simplification
- Transistor sizing
- Schematic capture
- Custom layout
- Parasitic extraction
IV. Verification
- Design-rule checking (DRC).
- Layout-versus-schematic checking (LVS).
- Post-layout analysis using extracted parasitics.
V. Reported results
- Completed the stated schematic-to-layout implementation flow.
- Closed DRC, LVS, and PEX for the design.
VI. Artifacts and data availability
The résumé establishes the following artifact classes. Public-safe figures and report excerpts will be attached after review:
- Schematic
- Layout
- DRC/LVS reports
- Extracted view
- Post-layout waveform